MT40A256M16GE-075EAUT Datasheet, PDF (60/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 6
Mode Register 6
Mode register 6 (MR6) controls various device operating modes as shown in the follow-
ing register definition table. Not all settings listed may be available on a die; only set-
tings required for speed bin support are available. MR6 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The map-
ping of address pins during the MRS command is shown in the following MR6 Register
Definition table.
Table 21: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode 21 20 19 18 17 – – – 13 12 11 10 9 8 7 6 5 4 3 2 1 0
register
Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 22: MR6 Register Definition
Mode
Register
21
20:18
17
13
12:10
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
NA on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
RFU
0 = Must be programmed to 0
1 = Reserved
t_{CCD_L}
000 = 4 clocks (≤1333 Mb/s)
001 = 5 clocks (>1333 Mb/s and ≤1866 Mb/s)
010 = 6 clocks (>1866 Mb/s and ≤2400 Mb/s)
011 = 7 clocks (>2400 Mb/s and ≤2666 Mb/s)
100 = 8 clocks (>2666 Mb/s and ≤3200 Mb/s)
101 = Reserved
110 = Reserved
111 = Reserved
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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