MT40A256M16GE-075EAUT Datasheet, PDF (49/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 2
CAS WRITE Latency
CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Defini-
tion table. CWL is the delay, in clock cycles, between the internal WRITE command and
the availability of the first bit of input data. The device does not support any half-clock
latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity la-
tency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.
Low-Power Auto Self Refresh
Low-power auto self refresh (LPASR) is supported in the device. Applications requiring
SELF REFRESH operation over different temperature ranges can use this feature to opti-
mize the I_DD6 current for a given temperature range as specified in the MR2 Register
Definition table.
Dynamic ODT
In certain applications and to further enhance signal integrity on the data bus, it is de-
sirable to change the termination strength of the device without issuing an MRS com-
mand. This may be done by configuring the dynamic ODT (R_TT(WR)) settings in
MR2[11:9]. In write leveling mode, only R_TT(NOM) is available.
Write Cyclic Redundancy Check Data Bus
The write cyclic redundancy check (CRC) data bus feature during writes has been added
to the device. When enabled via the mode register, the data transfer size goes from the
normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for
the CRC information.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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