MT40A256M16GE-075EAUT Datasheet, PDF (89/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
Figure 30: MPR READ Timing
CK_c
CK_t
Command
Address
T0
Ta0
Ta1
MPE Enable
PREA
MRS¹
DES
t_RP
t_MOD
Valid
Valid
Valid
Tb0
READ
Add²
Tc0
DES
Valid
Tc1
DES
Valid
Tc2
DES
Valid
Tc3
DES
Valid
Td0
DES
Valid
Td1
Te0
Tf0
Tf1
MPE Disable
DES
MRS³
Valid⁴
t_MPRR
t_MOD
Valid
Valid
Valid
DES
Valid
CKE
DQS_t,
DQS_c
DQ
PL⁵ + AL + CL
UI0 UI1 UI2 UI5 UI6 UI7
Time Break
Don’t Care
Notes:
1. ^tCCD_S = 4^tCK, Read Preamble = 1^tCK.
2. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7)
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t
Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01
3. Multipurpose registers read/write disable (MR3 A2 = 0).
4. Continue with regular DRAM command.
5. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
Figure 31: MPR Back-to-Back READ Timing
T0
T1
T2
T3
T4
T5
T6
Ta0
CK_c
CK_t
Command DES
Address Valid
READ
Add²
DES
DES
t_{CCD_S}1
Valid
Add²
DES
Valid
READ
DES
Valid
Valid
DES
Valid
CKE
DQS_t,
DQS_c
DQ
DQS_t,
DQS_c
DQ
PL³ + AL + CL
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Ta9
DES
DES
DES
DES
DES
DES
DES
DES
DES
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
UI0 UI1 UI2 UI3
UI0 UI1 UI2 UI3
Ta10
DES
Valid
Time Break
Notes: 1. ^tCCD_S = 4^tCK, Read Preamble = 1^tCK.
2. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
Don’t Care
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
89
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