MT40A256M16GE-075EAUT Datasheet, PDF (108/359 Pages) Micron Technology – Automotive DDR4 SDRAM

Figure 55: CA Parity Flow Diagram
CA
process start
MR5[2:0] set parity latency (PL)
MR5[4] set parity error status to 0
MR5[9] enable/disable persistent mode
CA
latched in
CA parity ^Yes
enabled
Persistent _Yes
mode
enabled
No
No
MR5[4] = 0 _Yes
@ ADDR/CMD
latched
No
Yes
CA error
No
Good CA
processed
Bad CA
processed
CA parity ^Yes
error
No
Good CA
processed
Ignore
bad CMD
ALERT_n LOW
44 to 144 CKs
Command
execution
unknown
Log error/
set parity status
Internal
precharge all
Normal
operation ready
Operation ready?
ALERT_n HIGH
Command
execution
unknown
CA parity ^Yes
error
No
Good CA
processed
Ignore
bad CMD
Command
execution
unknown
ALERT_n LOW
44 to 144 CKs
MR5[4] = 0 Yes
@ ADDR/CMD
latched
No
Internal
precharge all
Log error/
set parity status
ALERT_n HIGH
Command
execution
unknown
Normal operation ready
MR5[4] reset to 0 if desired
Normal operation ready
MR5[4] reset to 0 if desired