MT40A256M16GE-075EAUT Datasheet, PDF (216/359 Pages) Micron Technology – Automotive DDR4 SDRAM

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4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 160: ^tWPST Method for Calculating Transitions and Endpoints
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Notes: 1. V_sw1 =(0.9) × V_IL,diff,DQS.
2. V_sw2 = (0.1) × V_IL,diff,DQS.
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Write Timing – Data Strobe-to-Data Relationship
The DQ input receiver uses a compliance mask (Rx) for voltage and timing as shown in
the figure below. The receiver mask (Rx mask) defines the area where the input signal
must not encroach in order for the DRAM input receiver to be able to successfully cap-
ture a valid input signal. The Rx mask is not the valid data-eye. TdiVW and V _diVW define
the absolute maximum Rx mask.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
216
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