MT40A256M16GE-075EAUT Datasheet, PDF (228/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 176: WRITE (BC4) OTF to WRITE (BL8) with 1^tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command WRITE
DES
DES
DES
WRITE
DES
Bank Group
BGa
Address
Address
Bank
Col n
t_{CCD_S = 4}
BGb
Bank
Col b
DQS_t,
DQS_c
DQ
WL = AL + CWL = 9
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_WR
4 Clocks
t_WTR
t_WPRE
t_WPST
t_WPRE
t_WPST
DI DI DI DI
n n+1 n+2 n+3
WL = AL + CWL = 9
DI DI DI DI DI DI DI DI
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
WRITE Operation Followed by READ Operation
Figure 177: WRITE (BL8) to READ (BL8) with 1^tCK Preamble in Different Bank Group
T0
T1
T7
CK_c
CK_t
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
DES
t_WPRE
DES
DES
DES
4 Clocks
DES
DES
READ
t_{WTR_S = 2}
BGb
t_WPST
Bank
Col b
WL = AL + CWL = 9
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
DES
DES
DES
DES
DES
DES
DES
t_RPRE
RL = AL + CL = 11
DI DI DI DI DI DI DI
b b+1 b+2 b+3 b+4 b+5 b+6
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1^tCK, WRITE preamble =
1^tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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