MT40A256M16GE-075EAUT Datasheet, PDF (51/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 3
Table 16: MR3 Register Definition (Continued)
Mode
Register
10:9
8:6
5
4
3
2
1:0
Description
WRITE CMD latency when CRC/DM enabled
00 = 4CK (DDR4-1600)
01 = 5CK (DDR4-1866/2133/2400/2666)
10 = 6CK (DDR4-2933/3200)
11 = Reserved
Fine granularity refresh mode
000 = Normal mode (fixed 1x)
001 = Fixed 2x
010 = Fixed 4x
011 = Reserved
100 = Reserved
101 = On-the-fly 1x/2x
110 = On-the-fly 1x/4x
111 = Reserved
Temperature sensor status
0 = Disabled
1 = Enabled
Per-DRAM addressability
0 = Normal operation (disabled)
1 = Enable
Gear-down mode – Ratio of internal clock to external data rate
0 = [1:1]; (1/2 rate data)
1 = [2:1]; (1/4 rate data)
Multipurpose register (MPR) access
0 = Normal operation
1 = Data flow from MPR
MPR page select
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3 (restricted for DRAM manufacturer use only)
Multipurpose Register
The multipurpose register (MPR) is used for several features:
• Readout of the contents of the MRn registers
• WRITE and READ system patterns used for data bus calibration
• Readout of the error frame when the command address parity feature is enabled
To enable MPR, issue an MRS command to MR3[2] = 1. MR3[12:11] define the format of
read data from the MPR. Prior to issuing the MRS command, all banks must be in the
idle state (all banks precharged and ^tRP met). After MPR is enabled, any subsequent RD
or RDA commands will be redirected to a specific mode register.
The mode register location is specified with the READ command using address bits. The
MR is split into upper and lower halves to align with a burst length limitation of 8. Pow-
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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