MT40A256M16GE-075EAUT Datasheet, PDF (52/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 3
er-down mode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA com-
mands are not allowed during MPR mode. The RESET function is supported during
MPR mode, which requires device re-initialization.
WRITE Command Latency When CRC/DM is Enabled
The WRITE command latency (WCL) must be set when both write CRC and DM are en-
abled for write CRC persistent mode. This provides the extra time required when com-
pleting a WRITE burst when write CRC and DM are enabled. This means at data rates
less than or equal to 1600 MT/s then 4nCK is used, 5nCK or 6nCK are not allowed; at
data rates greater than 1600 MT/s and less than or equal to 2666 MT/s then 5nCK is
used, 4nCK or 6nCK are not allowed; and at data rates greater than 2666 MT/s and less
than or equal to 3200 MT/s then 6nCK is used; 4nCK or 5nCK are not allowed.
Fine Granularity Refresh Mode
This mode had been added to DDR4 to help combat the performance penalty due to
refresh lockout at high densities. Shortening ^tRFC and increasing cycle time allows more
accesses to the chip and can produce higher bandwidth.
Temperature Sensor Status
This mode directs the DRAM to update the temperature sensor status at MPR Page 2,
MPR0 [4,3]. The temperature sensor setting should be updated within 32ms; when an
MPR read of the temperature sensor status bits occurs, the temperature sensor status
should be no older than 32ms.
Per-DRAM Addressability
This mode allows commands to be masked on a per device basis providing any device
in a rank (devices sharing the same command and address signals) to be programmed
individually. As an example, this feature can be used to program different ODT or V_REF
values on DRAM devices within a given rank.
Gear-Down Mode
The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS com-
mand followed by a sync pulse to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. For operation in 1/2 rate mode,
no MRS command or sync pulse is required.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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