MT40A256M16GE-075EAIT Datasheet, PDF (63/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Truth Tables
Notes: 1. • BG = Bank group address
• BA = Bank address
• RA = Row address
• CA = Column address
• BC_n = Burst chop
• X = “Don’t Care”
• V = Valid
2. All DDR4 SDRAM commands are defined by states of CS_n, ACT_n, RAS_n/A16, CAS_n/
A15, WE_n/A14, and CKE at the rising edge of the clock. The MSB of BG, BA, RA, and CA
are device density- and configuration-dependent. When ACT_n = H, pins RAS_n/A16,
CAS_n/A15, and WE_n/A14 are used as command pins RAS_n, CAS_n, and WE_n, respec-
tively. When ACT_n = L, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as address
pins A16, A15, and A14, respectively.
3. RESET_n is enabled LOW and is used only for asynchronous reset and must be main-
tained HIGH during any function.
4. Bank group addresses (BG) and bank addresses (BA) determine which bank within a
bank group is being operated upon. For MRS commands, the BG and BA selects the spe-
cific mode register location.
5. V means HIGH or LOW (but a defined logic level), and X means either defined or unde-
fined (such as floating) logic level.
6. READ or WRITE bursts cannot be terminated or interrupted, and fixed/on-the-fly (OTF)
BL will be defined by MRS.
7. During an MRS command, A17 is RFU and is device density- and configuration-depend-
ent.
8. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh.
9. V_PP and V_REF (V_REFCA) must be maintained during SELF REFRESH operation.
10. Refer to the Truth Table – CKE table for more details about CKE transition.
11. Controller guarantees self refresh exit to be synchronous. DRAM implementation has
the choice of either synchronous or asynchronous.
12. The NO OPERATION (NOP) command may be used only when exiting maximum power
saving mode or when entering gear-down mode.
13. The NOP command may not be used in place of the DESELECT command.
14. The power-down mode does not perform any REFRESH operation.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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