MT40A256M16GE-075EAIT Datasheet, PDF (208/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
2. DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from col-
umn n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable.
READ Operation with Command/Address Parity (CA Parity)
Figure 152: Consecutive READ (BL8) with 1^tCK Preamble and CA Parity in Different Bank Group
T0
CK_c
CK_t
T1
T2
T3
T4
T7
T8
T13
T14
T15
T16
T17
T18
T19
T20
T21
T20
T21
Command READ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S = 4}
Bank Group _BGa
BGb
Address
Address
Parity
Bank
Col n
DQS_t,
DQS_c
DQ
Bank
Col b
RL = 15
t_RPRE
t_RPST
RL = 15
DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO
n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 b b + 1 b + 2 b + 3 b +4 _ b + 5 b + 6 b + 7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1^tCK.
2. DO n (or b) = data-out from column n (or b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during
READ commands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
208
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