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| MT40A256M16GE-075EAIT Datasheet, PDF (261/359 Pages) Micron Technology – Automotive DDR4 SDRAM | |||
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4Gb: x8, x16 Automotive DDR4 SDRAM
Electrical Characteristics â AC and DC Single-Ended Input
Measurement Levels
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)
Parameter
DC input high voltage
DC input low voltage
AC input low voltage
Reference voltage for CMD/ADDR inputs
Symbol
VIH(DC)
VIL(DC)
VIL(AC)
VREFFCA(DC)
Min
VREF + 75
VSS
VSS5
0.49 Ã VDD
Max
VDD
VREF - 75
VREF - 100
0.51 Ã VDD
Unit
mV
mV
mV
V
Note
1, 2
1, 2
1, 2, 3
4
Notes:
1. For input except RESET_n. VREF = VREFCA(DC).
2. VREF = VREFCA(DC).
3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to âOvershoot and Undershoot Specifications.â
Table 85: Command and Address Input Levels: DDR4-2666
Parameter
AC input high voltage
DC input high voltage
DC input low voltage
AC input low voltage
Reference voltage for CMD/ADDR inputs
Symbol
VIH(AC)
VIH(DC)
VIL(DC)
VIL(AC)
VREFFCA(DC)
Min
VREF + 90
VREF + 65
VSS
VSS5
0.49 Ã VDD
Max
VDD5
VDD
VREF - 65
VREF - 90
0.51 Ã VDD
Unit
mV
mV
mV
mV
V
Note
1, 2, 3
1, 2
1, 2
1, 2, 3
4
Notes:
1. For input except RESET_n. VREF = VREFCA(DC).
2. VREF = VREFCA(DC).
3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to âOvershoot and Undershoot Specifications.â
Table 86: Command and Address Input Levels: DDR4-2933 and DDR4-3200
Parameter
AC input high voltage
DC input high voltage
DC input low voltage
AC input low voltage
Reference voltage for CMD/ADDR inputs
Symbol
VIH(AC)
VIH(DC)
VIL(DC)
VIL(AC)
VREFFCA(DC)
Min
VREF + 90
VREF + 65
VSS
VSS5
0.49 Ã VDD
Max
VDD5
VDD
VREF - 65
VREF - 90
0.51 Ã VDD
Unit
mV
mV
mV
mV
V
Note
1, 2, 3
1, 2
1, 2
1, 2, 3
4
Notes:
1. For input except RESET_n. VREF = VREFCA(DC).
2. VREF = VREFCA(DC).
3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to âOvershoot and Undershoot Specifications.â
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
261
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
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