MT40A256M16GE-075EAIT Datasheet, PDF (53/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 4
Mode Register 4
Mode register 4 (MR4) controls various device operating modes as shown in the follow-
ing register definition table. Not all settings listed may be available on a die; only set-
tings required for speed bin support are available. MR4 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The map-
ping of address pins during the MRS command is shown in the following MR4 Register
Definition table.
Table 17: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bus
_n _n _n
Mode 21 20 19 18 17 – – – 13 12 11 10 9 8 7 6 5 4 3 2 1 0
register
Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command.
Table 18: MR4 Register Definition
Mode
Register
21
20:18
17
13
12
11
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
Hard Post Package Repair (hPPR mode)
0 = Disabled
1 = Enabled
WRITE preamble setting
0 = 1^tCK toggle¹
1 = 2^tCK toggle
READ preamble setting
0 = 1^tCK toggle¹
1 = 2^tCK toggle (When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value at
least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK range.)
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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