MT40A256M16GE-075EAIT Datasheet, PDF (170/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Data Bus Inversion
Data Bus Inversion
The DATA BUS INVERSION (DBI) function is supported only for x8 and x16 configura-
tions (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in
conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given
DQS strobe edge. The DBI function shares a common pin with the DATA MASK (DM)
and TDQS functions. The DBI function applies to either or both READ and WRITE oper-
ations: Write DBI cannot be enabled at the same time the DM function is enabled, and
DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM,
and DBI functions are shown below.
Table 60: DBI vs. DM vs. TDQS Function Matrix
Read DBI
Enabled (or Disabled)
MR5[12]=1 (or
MR5[12] = 0)
Disabled
MR5[12] = 0
Write DBI
Disabled
MR5[11] = 0
Enabled
MR5[11] = 1
Disabled
MR5[11] = 0
Disabled
MR5[11] = 0
Data Mask (DM)
Disabled
MR5[10] = 0
Disabled
MR5[10] = 0
Enabled
MR5[10] = 1
Disabled
MR5[10] = 0
TDQS (x8 only)
Disabled
MR1[11] = 0
Disabled
MR1[11] = 0
Disabled
MR1[11] = 0
Enabled
MR1[11] = 1
DBI During a WRITE Operation
If DBI_n is sampled LOW on a given byte lane during a WRITE operation, the DRAM in-
verts write data received on the DQ inputs prior to writing the internal memory array. If
DBI_n is sampled HIGH on a given byte lane, the DRAM leaves the data received on the
DQ inputs noninverted. The write DQ frame format is shown below for x8 and x16 con-
figurations (the x4 configuration does not support the DBI function).
Table 61: DBI Write, DQ Frame Format (x8)
Function
DQ[7:0]
DM_n or
DBI_n
0
Byte 0
DM0 or
DBI0
1
Byte 1
DM1 or
DBI1
2
Byte 2
DM2 or
DBI2
Transfer
3
4
Byte 3
Byte 4
DM3 or
DBI3
DM4 or
DBI4
5
Byte 5
DM5 or
DBI5
6
Byte 6
DM6 or
DBI6
7
Byte 7
DM7 or
DBI7
Table 62: DBI Write, DQ Frame Format (x16)
Function
DQ[7:0]
LDM_n or
LDBI_n
DQ[15:8]
0
LByte 0
LDM0 or
LDBI0
UByte 0
1
LByte 1
LDM1 or
LDBI1
UByte 1
Transfer, Lower (L) and Upper(U)
2
3
4
5
LByte 2
LByte 3
LByte 4
LByte 5
LDM2 or
LDBI2
LDM3 or
LDBI3
LDM4 or
LDBI4
LDM5 or
LDBI5
UByte 2
UByte 3
UByte 4
UByte 5
6
LByte 6
LDM6 or
LDBI6
UByte 6
7
LByte 7
LDM7 or
LDBI7
UByte 7
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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