MT40A256M16GE-075EAIT Datasheet, PDF (205/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 147: READ to PRECHARGE with 2^tCK Preamble
T0
T1
T2
T3
T6
T7
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_c
CK_t
Command DES
READ
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
DES
DES
DES
Bank Group
Address
Address
BGa
Bank a
Col n
BC4 Opertaion
DQS_t,
DQS_c
DQ
BL8 Opertaion
DQS_t,
DQS_c
DQ
BGa or
BGb
t_RTP
Bank a
(or all)
RL = AL + CL
t_RP
DO DO DO DO
n n+1 n+2 n+3
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
BGa
Bank a
Row b
Time Break
Transitioning Data
Don’t Care
Notes:
1. RL = 11 (CL = 11, AL = 0 ), Preamble = 2^tCK, ^tRTP = 6, ^tRP = 11.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. The example assumes that ^tRAS (MIN) is satisfied at the PRECHARGE command time (T7)
and that ^tRC (MIN) is satisfied at the next ACTIVATE command time (T18).
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 148: READ to PRECHARGE with Additive Latency and 1^tCK Preamble
T0
T1
T2
T3
T10
T11
T12
T13
T16
T19
T20
T21
T22
T23
T24
T25
T26
T27
CK_c
CK_t
Command DES
READ
DES
DES
DES
DES
DES
DES
PRE
DES
DES
DES
DES
DES
DES
DES
DES
ACT
Bank Group
Address
Address
BGa
Bank a
Col n
BC4 Opertaion
DQS_t,
DQS_c
DQ
BL8 Opertaion
DQS_t,
DQS_c
DQ
AL = CL - 2 = 9
BGa or
BGb
t_RTP
CL = 11
Bank a
(or all)
t_RP
DO DO DO DO
n n+1 n+2 n+3
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
BGa
Bank a
Row b
Time Break
Notes: 1. RL =20 (CL = 11, AL = CL - 2), Preamble = 1^tCK, ^tRTP = 6, ^tRP = 11.
2. DO n = data-out from column n.
Transitioning Data
Don’t Care
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
205
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.