MT40A256M16GE-075EAIT Datasheet, PDF (230/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 179: WRITE (BC4) OTF to READ (BC4) OTF with 1^tCK Preamble in Different Bank Group
T0
T1
T7
CK_c
CK_t
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
DES
DES
DES
DES
4 Clocks
WL = AL + CWL = 9
t_WPRE
t_WPST
DI DI DI DI
n n+1 n+2 n+3
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
t_{WTR_S = 2}
BGb
Bank
Col b
t_RPRE
t_RPST
RL = AL + CL = 11
DI DI DI DI
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1^tCK, WRITE preamble =
1^tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (^tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 180: WRITE (BC4) OTF to READ (BC4) OTF with 1^tCK Preamble in Same Bank Group
T0
T1
T7
CK_c
CK_t
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T26
T27
T28
T29
Command WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
Bank Group
BGa
Address
4 Clocks
t_{WTR_L = 4}
BGa
Address
Bank
Col n
DQS_t,
DQS_c
DQ
WL = AL + CWL = 9
t_WPRE
t_WPST
DI DI DI DI
n n+1 n+2 n+3
Bank
Col b
t_RPRE
RL = AL + CL = 11
DI DI DI
b b+1 b+2
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1^tCK, WRITE preamble =
1^tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T17.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
230
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.