MT40A256M16GE-075EAIT Datasheet, PDF (54/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Mode Register 4
Table 18: MR4 Register Definition (Continued)
Mode
Register
10
9
8:6
5
4
3
2
1
0
Description
READ preamble training
0 = Disabled
1 = Enabled
Self refresh abort mode
0 = Disabled
1 = Enabled
CMD (CAL) address latency
000 = 0 clocks (disabled)
001 =3 clocks¹
010 = 4 clocks
011 = 5 clocks¹
100 = 6 clocks
101 = 8 clocks
110 = Reserved
111 = Reserved
soft Post Package Repair (sPPR mode)
0 = Disabled
1 = Enabled
Internal V_REF monitor
0 = Disabled
1 = Enabled
Temperature controlled refresh mode
0 = Disabled
1 = Enabled
Temperature controlled refresh range
0 = Normal temperature mode
1 = Extended temperature mode
Maximum power savings mode
0 = Normal operation
1 = Enabled
RFU
0 = Must be programmed to 0
1 = Reserved
Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.
Hard Post Package Repair Mode
The hard post package repair (hPPR) mode feature is JEDEC optional for 4Gb DDR4
memories. Performing an MPR read to page 2 MPR0 [7] indicates whether hPPR mode is
available (A7 = 1) or not available (A7 = 0). hPPR mode provides a simple and easy repair
method of the device after placed in the system. One row per bank can be repaired. The
repair process is irrevocable so great care should be exercised when using.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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