MT40A256M16GE-075EAIT Datasheet, PDF (37/359 Pages) Micron Technology – Automotive DDR4 SDRAM

Figure 11: ^tMRD Timing
CK_c
CK_t
Command
T0
Valid
T1
Valid
T2
Valid
Address
Valid
Valid
Valid
CKE
Settings
Old settings
Ta0
MRS²
Valid
Ta1
DES
Valid
4Gb: x8, x16 Automotive DDR4 SDRAM
Programming Mode Registers
Tb0
DES
Valid
Tb1
DES
Valid
Tb2
DES
Valid
t_MRD
Updating settings
Tc0
DES
Valid
Tc1
MRS²
Valid
Tc2
Valid
Valid
Time Break
Don’t Care
Notes:
1. This timing diagram depicts CA parity mode “disabled” case.
2. ^tMRD applies to all MRS commands with the following exceptions:
Gear-down mode
CA parity mode
CAL mode
Per-DRAM addressability mode
V_REFDQ training value, V_REFDQ training mode, and V_REFDQ training range
The MRS command to nonMRS command delay, ^tMOD, is required for the DRAM to
update features, except for those noted in note 2 in figure below where the individual
function descriptions may specify a different requirement. ^tMOD is the minimum time
required from an MRS command to a nonMRS command, excluding DES, as shown in
the ^tMOD Timing figure.
Figure 12: ^tMOD Timing
CK_c
CK_t
Command
T0
Valid
T1
Valid
T2
Valid
Address
Valid
Valid
Valid
CKE
Settings
Old settings
Ta0
MRS²
Valid
Ta1
DES
Valid
Ta2
DES
Valid
Ta3
DES
Valid
Ta4
DES
Valid
t_MOD
Updating settings
Tb0
DES
Valid
Tb1
Valid
Valid
Tb2
Valid
Valid
New settings
Time Break
Don’t Care
Notes:
1. This timing diagram depicts CA parity mode “disabled” case.
2. ^tMOD applies to all MRS commands with the following exceptions:
DLL enable, DLL RESET, Gear-down mode
V_REFDQ training value, internal V_REF training monitor, V_REFDQ training mode, and V_REFDQ
training range
Maximum power savings mode , Per-DRAM addressability mode, and CA parity mode
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
37
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