MT40A256M16GE-075EAIT Datasheet, PDF (105/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Command/Address Parity
Figure 49: CA Parity Error Checking – SRX Attempt
T0
CK_c
CK_t
Command/
Address
SRX¹
t_IS
CKE
Ta0
Ta1
Tb0
Tb1
Tc0
DES
DES
Error²
Valid²
Valid²
t_{PAR_UNKNOWN}
t_{PAR_ALERT_ON}
ALERT_n
t_{XS_FAST}8
t_XS
t_XSDLL
Tc1
Tc2
Td0
Td1
Te0
Tf0
Valid²
DES^{2, 3}
DES^{2, 3}
Valid^{2, 4, 5}
t > 2nCK t > 1nCK + 3ns
Valid^{2, 4, 6}
Valid^{2, 4, 7}
t_{PAR_ALERT_PW}
SRX¹
DES Valid^{3, 5} _{Command execution unknown}
Error
Valid _{Command not executed}
Valid^4,5,6,7 Command executed
Time Break
Don’t Care
Notes:
1. Self refresh abort = disable: MR4 [9] = 0.
2. Input commands are bounded by ^tXSDLL, ^tXS, ^tXS_ABORT, and ^tXS_FAST timing.
3. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
4. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking off until parity error status bit cleared.
5. Only an MRS (limited to those described in the SELF REFRESH Operation section), ZQCS,
or ZQCL command is allowed.
6. Valid commands not requiring a locked DLL.
7. Valid commands requiring a locked DLL.
8. This figure shows the case from which the error occurred after ^tXS_FAST. An error may
also occur after ^tXS_ABORT and ^tXS.
Figure 50: CA Parity Error Checking – PDE/PDX
T0
CK_c
CK_t
T1
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
Td1
Td2
Td3
Te0
Te1
t_{CPDED + PL}
t_{XP + PL}
Command/
Address
CKE
Error²
t_IH
DES¹
t_IS
DES¹
t_{PAR_ALERT_ON}
DES⁵
t_IS
DES⁵
t_{PAR_ALERT_PW}1
t > 2nCK
DES⁴
Valid³
t > 1nCK + 3ns
ALERT_n
DES⁴
Error²
Valid³
DES⁵ _{Command execution unknown}
DES¹ Command not executed
Command executed
Don’t Care
Time Break
Notes:
1. Only DESELECT command is allowed.
2. Error could be precharge or activate.
3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity
checking is off until parity error status bit cleared.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
105
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