PIC16F688 Datasheet, PDF (99/174 Pages) Microchip Technology – 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F688
10.5 USART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the RC4/C2OUT/TX/CK pin
(instead of being supplied internally in Master mode).
This allows the device to transfer or receive data while
in any Low-power mode.
10.5.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Addr Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Ch PIR1
EEIF
ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
11h BAUDCTL ABDOVF RCIDL — SCKP BRG16 —
WUE ABDEN 00-0 0-00 00-0 0-00
12h SPBRGH USART Baud Rate High Generator
0000 0000 0000 0000
13h SPBRG USART Baud Rate Generator
0000 0000 0000 0000
14h RCREG USART Receive Register
0000 0000 0000 0000
15h TXREG USART Transmit Register
0000 0000 0000 0000
16h TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
17h RCSTA
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X
8Ch PIE1
EEIE
ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.
 2004 Microchip Technology Inc.
Preliminary
DS41203B-page 97