PIC16F688 Datasheet, PDF (75/174 Pages) Microchip Technology – 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F688
9.1.2
READING THE DATA EEPROM
MEMORY
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>), and then set control bit RD
(EECON1<0>). The data is available in the very next
cycle, in the EEDAT register; therefore, it can be read
in the next instruction. EEDAT will hold this value until
another read or until it is written to by the user (during
a write operation).
EXAMPLE 9-1: DATA EEPROM READ
BSF
BCF
MOVLW
MOVWF
BCF
BSF
MOVF
STATUS, RP0 ;
STATUS, RP1 ; Bank 1
DATA_EE_ADDR ;
EEADR
; Data Memory
; Address to read
EECON1, EEPGD ; Point to DATA
; memory
EECON1, RD ; EE Read
EEDAT, W
; W = EEDAT
9.1.3
WRITING TO THE DATA EEPROM
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 9-2: DATA EEPROM WRITE
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
STATUS, RP0 ;
STATUS, RP1 ; Bank 1
DATA_EE_ADDR ;
EEADR
; Data Memory Address to write
DATA_EE_DATA ;
EEDAT
; Data Memory Value to write
EECON1, EEPGD ; Point to DATA memory
EECON1, WREN ; Enable writes
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable INTs.
SLEEP
; Wait for interrupt to signal write complete
BCF
EECON1, WREN ; Disable writes
 2004 Microchip Technology Inc.
Preliminary
DS41203B-page 73