PIC16F688 Datasheet, PDF (11/174 Pages) Microchip Technology – 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F688
TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOD
Reset
Value on
all other
Resets⁽¹⁾
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0
Timer0 Module’s register
xxxx xxxx uuuu uuuu
02h PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
04h FSR
Indirect Data Memory Address Pointer
xxxx xxxx uuuu uuuu
05h PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0 --xx xx00 --uu uuuu
06h
—
Unimplemented
—
—
07h PORTC
—
—
RC5
RC4
RC3
RC2
RC1
RC0 --xx xx00 --uu uuuu
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 ---0 0000
0Bh INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF⁽²⁾ 0000 0000 0000 0000
0Ch PIR1
EEIF
ADIF
RCIF
C2IF
C1IF
OSFIF
TXIF
TMR1IF 0000 0000 0000 0000
0Dh
—
Unimplemented
—
—
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
10h T1CON
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h BAUDCTL ABDOVF RCIDL
—
SCKP
BRG16
—
WUE
ABDEN 01-0 0-00 01-0 0-00
12h SPBRGH USART Baud Rate High Generator
0000 0000 0000 0000
13h SPBRG USART Baud Rate Generator
0000 0000 0000 0000
14h RCREG USART Receive Register
0000 0000 0000 0000
15h TXREG USART Transmit Register
0000 0000 0000 0000
16h TXSTA
CSRC
TX9
TXEN
SYNC
SENDB BRGH
TRMT
TX9D 0000 0010 0000 0010
17h RCSTA
SPEN
RX9
SREN
CREN
ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
18h WDTCON
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
19h CMCON0 C2OUT C1OUT C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0000 0000 0000
1Ah CMCON1
—
—
—
—
—
—
T1GSS C2SYNC ---- --10 ---- --10
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG
—
CHS2
CHS1
CHS0 GO/DONE ADON 00-0 0000 00-0 0000
Legend:
Note 1:
2:
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon reset but will set again if the
mismatched exists.
 2004 Microchip Technology Inc.
Preliminary
DS41203B-page 9