PIC16F688 Datasheet, PDF (113/174 Pages) Microchip Technology – 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F688
FIGURE 11-8:
INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT ⁽³⁾
(4)
INT pin
INTF Flag
(1)
(INTCON<1>)
(1)
(5)
GIE bit
(INTCON<7>)
Interrupt Latency ⁽²⁾
Instruction Flow
PC
Instruction
Fetched
PC
Inst (PC)
PC + 1
Inst (PC + 1)
PC + 1
—
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
Executed
Inst (PC - 1)
Inst (PC)
Dummy Cycle
Dummy Cycle
Inst (0004h)
Note 1:
2:
3:
4:
5:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 14.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 11-6: SUMMARY OF INTERRUPT REGISTERS
Address Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh, 8Bh INTCON GIE
PEIE T0IE INTE RAIE T0IF
INTF RAIF 0000 0000 0000 0000
0Ch
PIR1
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
 2004 Microchip Technology Inc.
Preliminary
DS41203B-page 111