PIC16F688 Datasheet, PDF (156/174 Pages) Microchip Technology – 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F688
FIGURE 14-10: PIC16F688 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
Q4
A/D CLK
(TOSC/2)⁽¹⁾
131
130
1 TCY
A/D Data
9
8
7
6
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
1 TCY
GO
Sample
132
Sampling Stopped
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 14-11: PIC16F688 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature-40°C ≤ TA ≤ +125°C
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
130
TAD A/D Clock Period
1.6
—
—
µs TOSC-based, VREF ≥ 3.0V
3.0*
—
—
µs TOSC-based, VREF full range
130
TAD A/D Internal RC
ADCS<1:0> = 11 (RC mode)
Oscillator Period
3.0*
6.0
9.0*
µs At VDD = 2.5V
2.0*
4.0
6.0*
µs At VDD = 5.0V
131
TCNV Conversion Time
—
11
—
TAD Set GO bit to new data in A/D Result
(not including
Acquisition Time)⁽¹⁾
register
132
TACQ Acquisition Time
11.5
—
µs
5*
—
—
µs The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
voltage (as stored on CHOLD).
134
TGO Q4 to A/D Clock
Start
—
TOSC/2
—
— If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Table 8-1 for minimum conditions.
DS41203B-page 154
Preliminary
 2004 Microchip Technology Inc.