PIC16F688 Datasheet, PDF (92/174 Pages) Microchip Technology – 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F688
FIGURE 10-6:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
RCIDL
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Addr Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Ch PIR1
EEIF
ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
11h BAUDCTL ABDOVF RCIDL — SCKP BRG16 —
WUE ABDEN 00-0 0-00 00-0 0-00
12h SPBRGH USART Baud Rate High Generator
0000 0000 0000 0000
13h SPBRG USART Baud Rate Generator
0000 0000 0000 0000
14h RCREG USART Receive Register
0000 0000 0000 0000
15h TXREG USART Transmit Register
0000 0000 0000 0000
16h TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
17h RCSTA
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X
8Ch PIE1
EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.
DS41203B-page 90
Preliminary
 2004 Microchip Technology Inc.