PIC18LF2X_13 Datasheet, PDF (550/560 Pages) Microchip Technology – PIC18(L)F2X/45K50 USB Flash MCU Product Brief

PIC18(L)F2X/4XK22
Reception ......................................................... 291
Transmission .................................................... 288
Synchronous Slave Mode
Associated Registers, Receive ........................ 295
Reception ......................................................... 295
Transmission .................................................... 293
Extended Instruction Set
ADDFSR .................................................................. 416
ADDULNK ................................................................ 416
and Using MPLAB Tools .......................................... 422
CALLW ..................................................................... 417
Considerations for Use ............................................ 420
MOVSF .................................................................... 417
MOVSS .................................................................... 418
PUSHL ..................................................................... 418
SUBFSR .................................................................. 419
SUBULNK ................................................................ 419
Syntax ...................................................................... 415
F
Fail-Safe Clock Monitor .............................................. 44, 355
Fail-Safe Condition Clearing ...................................... 44
Fail-Safe Detection .................................................... 44
Fail-Safe Operation .................................................... 44
Reset or Wake-up from Sleep .................................... 44
Fast Register Stack ............................................................ 72
Fixed Voltage Reference (FVR)
Associated Registers ............................................... 344
Flash Program Memory ...................................................... 95
Associated Registers ............................................... 103
Control Registers ....................................................... 96
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ......................... 98
TBLPTR (Table Pointer) Register ...................... 98
Erase Sequence ...................................................... 100
Erasing ..................................................................... 100
Operation During Code-Protect ............................... 103
Reading ...................................................................... 99
Table Pointer
Boundaries Based on Operation ........................ 98
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing To ................................................................. 101
Protection Against Spurious Writes ................. 103
Unexpected Termination .................................. 103
Write Verify ...................................................... 103
G
GOTO ............................................................................... 394
H
Hardware Multiplier .......................................................... 111
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
High/Low-Voltage Detect ................................................. 349
Applications .............................................................. 352
Associated Registers ............................................... 353
Characteristics ......................................................... 446
Current Consumption ............................................... 351
Effects of a Reset ..................................................... 353
Operation ................................................................. 350
During Sleep .................................................... 353
Setup ........................................................................ 351
Start-up Time ........................................................... 351
DS41412F-page 550
Typical Low-Voltage Detect Application .................. 352
HLVD. See High/Low-Voltage Detect. ............................. 349
I
I²C Mode (MSSPx)
Acknowledge Sequence Timing .............................. 250
Bus Collision
During a Repeated Start Condition .................. 255
During a Stop Condition .................................. 256
Effects of a Reset .................................................... 251
I²C Clock Rate w/BRG ............................................. 258
Master Mode
Operation ......................................................... 242
Reception ........................................................ 248
Start Condition Timing ............................. 244, 245
Transmission ................................................... 246
Multi-Master Communication, Bus Collision and
Arbitration ........................................................ 252
Multi-Master Mode ................................................... 251
Read/Write Bit Information (R/W Bit) ....................... 227
Slave Mode
Transmission ................................................... 232
Sleep Operation ....................................................... 251
Stop Condition Timing ............................................. 250
ID Locations ............................................................. 355, 371
INCF ................................................................................ 394
INCFSZ ............................................................................ 395
In-Circuit Debugger .......................................................... 371
In-Circuit Serial Programming (ICSP) ...................... 355, 371
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 420
Indexed Literal Offset Mode ............................................. 420
Indirect Addressing ............................................................ 91
INFSNZ ............................................................................ 395
Instruction Cycle ................................................................ 74
Clocking Scheme ....................................................... 74
Instruction Flow/Pipelining ................................................. 74
Instruction Set .................................................................. 373
ADDLW .................................................................... 379
ADDWF .................................................................... 379
ADDWF (Indexed Literal Offset Mode) .................... 421
ADDWFC ................................................................. 380
ANDLW .................................................................... 380
ANDWF .................................................................... 381
BC ............................................................................ 381
BCF ......................................................................... 382
BN ............................................................................ 382
BNC ......................................................................... 383
BNN ......................................................................... 383
BNOV ...................................................................... 384
BNZ ......................................................................... 384
BOV ......................................................................... 387
BRA ......................................................................... 385
BSF .......................................................................... 385
BSF (Indexed Literal Offset Mode) .......................... 421
BTFSC ..................................................................... 386
BTFSS ..................................................................... 386
BTG ......................................................................... 387
BZ ............................................................................ 388
CALL ........................................................................ 388
CLRF ....................................................................... 389
CLRWDT ................................................................. 389
COMF ...................................................................... 390
CPFSEQ .................................................................. 390
CPFSGT .................................................................. 391
CPFSLT ................................................................... 391
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