PIC18LF2X_13 Datasheet, PDF (49/560 Pages) Microchip Technology – PIC18(L)F2X/45K50 USB Flash MCU Product Brief

PIC18(L)F2X/4XK22
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the pri-
mary clock occurs (see Figure 3-3). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 3-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3
SOSCI
OSC1
1
2
3
n-1 n
Clock Transition⁽¹⁾
CPU
Clock
Peripheral
Clock
Program
Counter
PC
Note 1: Clock transition typically occurs within 2-4 TOSC.
PC + 2
PC + 4
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3
SOSC
OSC1
PLL Clock
Output
TOST⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
SCS<1:0> bits Changed
TPLL⁽¹⁾
1 2 n-1 n
Clock
Transition⁽²⁾
OSTS bit Set
PC + 2
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
PC + 4
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DS41412F-page 49