PIC18LF2X_13 Datasheet, PDF (119/560 Pages) Microchip Technology – PIC18(L)F2X/45K50 USB Flash MCU Product Brief

PIC18(L)F2X/4XK22
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0
—
bit 7
R/W-0
ADIF
R-0
RC1IF
R-0
TX1IF
R/W-0
SSP1IF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’.
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
bit 5
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
bit 4
TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART1 transmit buffer is full
bit 3
SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared by software)
0 = TMR1 register did not overflow
Note 1: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Global Interrupt Enable bit, GIE/
GIEH of the INTCON register.
Note:
User software should ensure the appro-
priate interrupt flag bits are cleared prior
to enabling an interrupt and after servic-
ing that interrupt.
 2010-2012 Microchip Technology Inc.
DS41412F-page 119