PIC18LF2X_13 Datasheet, PDF (284/560 Pages) Microchip Technology – PIC18(L)F2X/45K50 USB Flash MCU Product Brief

PIC18(L)F2X/4XK22
16.4.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCONx register
starts the auto-baud calibration sequence
(Section 16.4.2 “Auto-baud Overflow”). While the
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPBRGx begins
counting up using the BRG counter clock as shown in
Table 16-6. The fifth rising edge will occur on the RXx/
DTx pin at the end of the eighth bit period. At that time,
an accumulated value totaling the proper BRG period
is left in the SPBRGHx:SPBRGx register pair, the
ABDEN bit is automatically cleared, and the RCxIF
interrupt flag is set. A read operation on the RCREGx
needs to be performed to clear the RCxIF interrupt.
RCREGx content should be discarded. When
calibrating for modes that do not use the SPBRGHx
register the user can verify that the SPBRGx register
did not overflow by checking for 00h in the SPBRGHx
register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 16-6. During ABD,
both the SPBRGHx and SPBRGx registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGHx
and SPBRGx registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 16.4.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the auto-
baud counter starts counting at one. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract one
from the SPBRGHx:SPBRGx register pair.
TABLE 16-6: BRG COUNTER CLOCK
RATES
BRG16 BRGH
BRG Base
Clock
BRG ABD
Clock
0
0
1
1
Note:
0
FOSC/64
FOSC/512
1
FOSC/16
FOSC/128
0
FOSC/16
FOSC/128
1
FOSC/4
FOSC/32
During the ABD sequence, SPBRGx and
SPBRGHx registers are both used as a
16-bit counter, independent of BRG16
setting.
FIGURE 16-6:
AUTOMATIC BAUD RATE CALIBRATION
BRG Value
RXx/DTx pin
XXXXh
0000h
Start
Edge #1
bit 0 ^{bit 1}
Edge #2
bit 2 ^{bit 3}
Edge #3
bit 4 ^{bit 5}
Edge #4
bit 6 ^{bit 7}
001Ch
Edge #5
Stop bit
BRG Clock
Set by User
ABDEN bit
RCIDL
RCxIF bit
(Interrupt)
Read
RCREGx
SPBRGx
XXh
SPBRGHx
XXh
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
Auto Cleared
1Ch
00h
DS41412F-page 284
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