PIC18F2455_07 Datasheet, PDF (421/430 Pages) Microchip Technology – 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
Prescaler, Timer2 ............................................................. 147
PRI_IDLE Mode ................................................................. 40
PRI_RUN Mode ................................................................. 36
Program Counter ............................................................... 58
PCL, PCH and PCU Registers ................................... 58
PCLATH and PCLATU Registers .............................. 58
Program Memory
and the Extended Instruction Set ............................... 75
Code Protection ....................................................... 303
Instructions ................................................................. 62
Two-Word .......................................................... 62
Interrupt Vector .......................................................... 57
Look-up Tables .......................................................... 60
Map and Stack (diagram) ........................................... 57
Reset Vector .............................................................. 57
Program Verification and Code Protection ....................... 302
Associated Registers ............................................... 302
Programming, Device Instructions ................................... 307
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 336
PUSH and POP Instructions .............................................. 59
PUSHL ............................................................................. 352
PWM (CCP Module)
Associated Registers ............................................... 148
Auto-Shutdown (CCP1 Only) ................................... 147
Duty Cycle ................................................................ 146
Example Frequencies/Resolutions .......................... 147
Period ....................................................................... 146
Setup for PWM Operation ........................................ 147
TMR2 to PR2 Match ................................................ 146
PWM (ECCP Module) ...................................................... 151
CCPR1H:CCPR1L Registers ................................... 151
Direction Change in Full-Bridge
Output Mode .................................................... 156
Duty Cycle ................................................................ 152
Effects of a Reset ..................................................... 161
Enhanced PWM Auto-Shutdown ............................. 158
Enhanced PWM Mode ............................................. 151
Example Frequencies/Resolutions .......................... 152
Full-Bridge Application Example .............................. 156
Full-Bridge Mode ...................................................... 155
Half-Bridge Mode ..................................................... 154
Half-Bridge Output Mode
Applications Example ...................................... 154
Operation in Power-Managed Modes ...................... 161
Operation with Fail-Safe Clock Monitor ................... 161
Output Configurations .............................................. 152
Output Relationships (Active-High) .......................... 153
Output Relationships (Active-Low) ........................... 153
Period ....................................................................... 151
Programmable Dead-Band Delay ............................ 158
Setup for PWM Operation ........................................ 161
Start-up Considerations ........................................... 160
TMR2 to PR2 Match ................................................ 151
Q
Q Clock .................................................................... 147, 152
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 41
RC_RUN Mode .................................................................. 37
RCALL ............................................................................. 337
RCON Register
Bit Status During Initialization .................................... 50
Reader Response ............................................................ 424
Register File ....................................................................... 65
Register File Summary ................................................ 67–70
Registers
ADCON0 (A/D Control 0) ......................................... 259
ADCON1 (A/D Control 1) ......................................... 260
ADCON2 (A/D Control 2) ......................................... 261
BAUDCON (Baud Rate Control) .............................. 240
BDnSTAT (Buffer Descriptor n Status,
CPU Mode) ...................................................... 173
BDnSTAT (Buffer Descriptor n Status,
SIE Mode) ....................................................... 174
CCP1CON (ECCP Control) ..................................... 149
CCPxCON (Standard CCPx Control) ...................... 141
CMCON (Comparator Control) ................................ 269
CONFIG1H (Configuration 1 High) .......................... 288
CONFIG1L (Configuration 1 Low) ........................... 287
CONFIG2H (Configuration 2 High) .......................... 290
CONFIG2L (Configuration 2 Low) ........................... 289
CONFIG3H (Configuration 3 High) .......................... 291
CONFIG4L (Configuration 4 Low) ........................... 292
CONFIG5H (Configuration 5 High) .......................... 293
CONFIG5L (Configuration 5 Low) ........................... 293
CONFIG6H (Configuration 6 High) .......................... 294
CONFIG6L (Configuration 6 Low) ........................... 294
CONFIG7H (Configuration 7 High) .......................... 295
CONFIG7L (Configuration 7 Low) ........................... 295
CVRCON (Comparator Voltage
Reference Control) .......................................... 275
DEVID1 (Device ID 1) .............................................. 296
DEVID2 (Device ID 2) .............................................. 296
ECCP1AS (Enhanced Capture/Compare/PWM
Auto-Shutdown Control) .................................. 159
ECCP1DEL (PWM Dead-Band Delay) .................... 158
EECON1 (Data EEPROM Control 1) ................... 81, 90
HLVDCON (High/Low-Voltage
Detect Control) ................................................ 279
INTCON (Interrupt Control) ....................................... 99
INTCON2 (Interrupt Control 2) ................................ 100
INTCON3 (Interrupt Control 3) ................................ 101
IPR1 (Peripheral Interrupt Priority 1) ....................... 106
IPR2 (Peripheral Interrupt Priority 2) ....................... 107
OSCCON (Oscillator Control) .................................... 32
OSCTUNE (Oscillator Tuning) ................................... 28
PIE1 (Peripheral Interrupt Enable 1) ....................... 104
PIE2 (Peripheral Interrupt Enable 2) ....................... 105
PIR1 (Peripheral Interrupt Request
(Flag) 1) ........................................................... 102
PIR2 (Peripheral Interrupt Request
(Flag) 2) ........................................................... 103
PORTE .................................................................... 123
RCON (Reset Control) ....................................... 44, 108
RCSTA (Receive Status and Control) ..................... 239
SPPCFG (SPP Configuration) ................................. 188
SPPCON (SPP Control) .......................................... 187
SPPEPS (SPP Endpoint Address
and Status) ...................................................... 191
SSPCON1 (MSSP Control 1, I²C Mode) ................. 204
SSPCON1 (MSSP Control 1, SPI Mode) ................ 195
SSPCON2 (MSSP Control 2, I²C
Master Mode) .................................................. 205
SSPCON2 (MSSP Control 2, I²C
Slave Mode) .................................................... 206
SSPSTAT (MSSP Status, I²C Mode) ...................... 203
SSPSTAT (MSSP Status, SPI Mode) ...................... 194
© 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 419