PIC18F2455_07 Datasheet, PDF (259/430 Pages) Microchip Technology – 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
20.4 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any power-managed
mode.
20.4.1 EUSART SYNCHRONOUS
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
5. If 9-bit transmission is desired, set bit TX9.
6. Enable the transmission by setting enable bit
TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Start transmission by loading data to the
TXREGx register.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
51
PIR1
SPPIF⁽¹⁾ ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
54
PIE1
SPPIE⁽¹⁾ ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1
SPPIP⁽¹⁾ ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
53
TXREG
EUSART Transmit Register
53
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
53
SPBRGH EUSART Baud Rate Generator Register High Byte
53
SPBRG
EUSART Baud Rate Generator Register Low Byte
53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 257