PIC18F2455_07 Datasheet, PDF (117/430 Pages) Microchip Technology – 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 10-3: PORTB I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O Type
Description
RB0/AN12/
INT0/FLT0/
SDI/SDA
RB0
AN12
0
OUT
DIG LATB<0> data output; not affected by analog input.
1
IN
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
IN
ANA A/D input channel 12.⁽¹⁾
INT0
1
IN
ST External interrupt 0 input.
FLT0
1
IN
ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
SDI
SDA
1
IN
ST SPI data input (MSSP module).
1
OUT
DIG I²C™ data output (MSSP module); takes priority over port data.
1
IN I²C/SMB I²C data input (MSSP module); input type depends on module setting.
RB1/AN10/
INT1/SCK/
SCL
RB1
AN10
0
OUT
DIG LATB<1> data output; not affected by analog input.
1
IN
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
IN
ANA A/D input channel 10.⁽¹⁾
INT1
1
IN
ST External interrupt 1 input.
SCK
0
OUT
DIG SPI clock output (MSSP module); takes priority over port data.
SCL
1
IN
ST SPI clock input (MSSP module).
0
OUT
DIG I²C clock output (MSSP module); takes priority over port data.
1
IN I²C/SMB I²C clock input (MSSP module); input type depends on module setting.
RB2/AN8/
INT2/VMO
RB2
AN8
0
OUT
DIG LATB<2> data output; not affected by analog input.
1
IN
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
IN
ANA A/D input channel 8.⁽¹⁾
INT2
1
IN
ST External interrupt 2 input.
VMO
0
OUT
DIG External USB transceiver VMO data output.
RB3/AN9/
RB3
0
OUT
DIG LATB<3> data output; not affected by analog input.
CCP2/VPO
1
IN
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
AN9
1
IN
ANA A/D input channel 9.⁽¹⁾
CCP2⁽²⁾
0
OUT
DIG CCP2 Compare and PWM output.
1
IN
ST CCP2 Capture input.
VPO
0
OUT
DIG External USB transceiver VPO data output.
RB4/AN11/
RB4
KBI0/CSSPP
AN11
0
OUT
DIG LATB<4> data output; not affected by analog input.
1
IN
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.⁽¹⁾
1
IN
ANA A/D input channel 11.⁽¹⁾
KBI0
1
CSSPP⁽⁴⁾
0
IN
OUT
TTL Interrupt-on-pin change.
DIG SPP chip select control output.
RB5/KBI1/
PGM
RB5
0
OUT
DIG LATB<5> data output.
1
IN
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1
1
IN
TTL Interrupt-on-pin change.
PGM
x
IN
ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
Legend:
Note 1:
2:
3:
4:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I²C/SMB = I²C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD operation is enabled.
40/44-pin devices only.
© 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 115