PIC18F2455_07 Datasheet, PDF (126/430 Pages) Microchip Technology – 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 10-9: PORTE I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O Type
Description
RE0/AN5/
CK1SPP
RE0
0
OUT DIG LATE<0> data output; not affected by analog input.
1
IN
ST PORTE<0> data input; disabled when analog input enabled.
AN5
1
IN
ANA A/D input channel 5; default configuration on POR.
CK1SPP
0
OUT DIG SPP clock 1 output (SPP enabled).
RE1/AN6/
CK2SPP
RE1
0
OUT DIG LATE<1> data output; not affected by analog input.
1
IN
ST PORTE<1> data input; disabled when analog input enabled.
AN6
1
IN
ANA A/D input channel 6; default configuration on POR.
CK2SPP
0
OUT DIG SPP clock 2 output (SPP enabled).
RE2/AN7/
OESPP
RE2
0
OUT DIG LATE<2> data output; not affected by analog input.
1
IN
ST PORTE<2> data input; disabled when analog input enabled.
AN7
1
IN
ANA A/D input channel 7; default configuration on POR.
MCLR/VPP/
RE3
OESPP
MCLR
VPP
0
—⁽¹⁾
— ⁽¹⁾
OUT
IN
IN
DIG
ST
ANA
SPP enable output (SPP enabled).
External Master Clear input; enabled when MCLRE Configuration bit
is set.
High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
RE3
— ⁽¹⁾
IN
ST PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTE
RDPU⁽³⁾
—
—
—
RE3^(1,2) RE2⁽³⁾
RE1⁽³⁾
RE0⁽³⁾
54
LATE⁽³⁾
—
—
—
—
—
LATE2 LATE1 LATE0
54
TRISE⁽³⁾
—
—
—
—
—
TRISE2 TRISE1 TRISE0
54
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
52
CMCON C2OUT C1OUT
SPPCON⁽³⁾
—
—
SPPCFG⁽³⁾ CLKCFG1 CLKCFG0
C2INV
—
CSEN
C1INV
—
CLK1EN
CIS
—
WS3
CM2
CM1
CM0
53
— SPPOWN SPPEN
55
WS2
WS1
WS0
55
Legend:
Note 1:
2:
3:
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
These registers or bits are unimplemented on 28-pin devices.
DS39632D-page 124
Preliminary
© 2007 Microchip Technology Inc.