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| PIC18F2455_07 Datasheet, PDF (253/430 Pages) Microchip Technology – 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology | |||
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PIC18F2455/2550/4455/4550
FIGURE 20-6:
EUSART RECEIVE BLOCK DIAGRAM
BRG16
x64 Baud Rate CLK
SPBRGH SPBRG
Baud Rate Generator
CREN
÷ 64
or
÷ 16
or
÷4
OERR
FERR
MSb
Stop (8)
RSR Register
7 â¢â¢â¢ 1
LSb
0 Start
Pin Buffer
and Control
Data
Recovery
RX
RXDTP
SPEN
Interrupt
RX9
RX9D
RCREG Register
FIFO
RCIF
RCIE
8
Data Bus
FIGURE 20-7:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED)
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Start
bit 7/8 Stop bit
bit
bit 7/8 Stop
bit
Word 1
RCREG
Word 2
RCREG
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
51
PIR1
SPPIF(1)
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1
SPPIE(1) ADIE
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1
SPPIP(1) ADIP
RCIP
TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
53
RCREG EUSART Receive Register
53
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
53
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16
â
WUE ABDEN
53
SPBRGH EUSART Baud Rate Generator Register High Byte
53
SPBRG
EUSART Baud Rate Generator Register Low Byte
53
Legend: â = unimplemented locations read as â0â. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 251
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