PIC18F2455_07 Datasheet, PDF (167/430 Pages) Microchip Technology – 28/40/44-Pin, High Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong
Buffer Pointers are set to the Even buffers. PPBRST
has to be cleared by firmware. This bit is ignored in
buffering modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing Resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on Resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0
specification.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry (i.e., voltage regulator) in a
low-power mode. The input clock to the SIE is also
disabled. This bit should be set by the software in
response to an IDLEIF interrupt. It should be reset by
the microcontroller firmware after an ACTVIF interrupt
is observed. When this bit is active, the device remains
attached to the bus but the transceiver outputs remain
Idle. The voltage on the VUSB pin may vary depending
on the value of this bit. Setting this bit before a IDLEIF
request will result in unpredictable bus behavior.
Note:
While in Suspend mode, a typical bus
powered USB device is limited to 500 μA
of current. This is the complete current
drawn by the PIC device and its support-
ing circuitry. Care should be taken to
assure minimum current draw when the
device enters Suspend mode.
17.2.2 USB CONFIGURATION REGISTER
(UCFG)
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 17-2). The separate USB
voltage regulator (see Section 17.2.2.8 “Internal
Regulator”) is controlled through the Configuration
registers.
The UFCG register contains most of the bits that
control the system level behavior of the USB module.
These include:
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage
The UCFG register also contains two bits which aid in
module testing, debugging and USB certifications.
These bits control output enable state monitoring and
eye pattern generation.
Note:
The USB speed, transceiver and pull-up
should only be configured during the mod-
ule setup phase. It is not recommended to
switch these settings while the module is
enabled.
17.2.2.1 Internal Transceiver
The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed compliant transceiver, internally con-
nected to the SIE. This feature is useful for low-cost
single chip applications. The UTRDIS bit (UCFG<3>)
controls the transceiver; it is enabled by default
(UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
transceiver speed; setting the bit enables full-speed
operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The USB specification requires 3.3V operation for
communications; however, the rest of the chip may be
running at a higher voltage. Thus, the transceiver is
supplied power from a separate source, VUSB.
17.2.2.2 External Transceiver
This module provides support for use with an off-chip
transceiver. The off-chip transceiver is intended for
applications where physical conditions dictate the loca-
tion of the transceiver to be away from the SIE. For
example, applications that require isolation from the
USB could use an external transceiver through some
isolation to the microcontroller’s SIE (Figure 17-2).
External transceiver operation is enabled by setting the
UTRDIS bit.
FIGURE 17-2:
TYPICAL EXTERNAL
TRANSCEIVER WITH
ISOLATION
PIC^®
Microcontroller
VDD Isolated
from USB
3.3V Derived
from USB
VDD
VUSB
VM
VP
RCV
VMO
VPO
UOE
Isolation
Transceiver
1.5 kΩ
D+
D-
Note: The above setting shows a simplified schematic
for a full-speed configuration using an external
transceiver with isolation.
© 2007 Microchip Technology Inc.
Preliminary
DS39632D-page 165