PIC18LF2XK22 Datasheet, PDF (38/42 Pages) Microchip Technology – Flash Memory Programming Specification

PIC18(L)F2XK22/4XK22
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/
VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Sym.
Characteristic
Min.
Max. Units
Conditions
D110 VIHH
D111 VDD
D112
D113
D031
D041
D080
D090
D012
IPP
IDDP
VIL
VIH
VOL
VOH
CIO
High-Voltage Programming Voltage on MCLR/VPP/RE3
Supply Voltage During Programming
PIC18LF
Programming Current on MCLR/VPP/RE3
Supply Current During Programming
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Capacitive Loading on I/O pin (PGD)
PIC18F
VDD + 4.5 9
1.80
3.60
V
V Row Erase/Write
2.7
3.60 V Bulk Erase operations
1.8
5.5
V Row Erase/Write
2.7
5.5
V Bulk Erase operations
—
300 A
—
10 mA
VSS 0.2 VDD V
0.8 VDD VDD
—
0.6
VDD – 0.7 —
—
50
V
V IOL = 8.5 mA @ 3.0V
V IOH = 3.0 mA @ 3.0V
pF To meet AC specifications
P1 TR
MCLR/VPP/RE3 Rise Time to enter Program/Verify mode
—
1.0 s (Note 1)
P2 TPGC Serial Clock (PGC) Period
100
—
ns VDD = 3.6V
1
—
s VDD = 1.8V
P2A TPGCL Serial Clock (PGC) Low Time
40
—
ns VDD = 3.6V
400
—
ns VDD = 1.8V
P2B TPGCH Serial Clock (PGC) High Time
40
—
ns VDD = 3.6V
400
—
ns VDD = 1.8V
P3 TSET1 Input Data Setup Time to Serial Clock 
15
—
ns
P4 THLD1 Input Data Hold Time from PGC
15
—
ns
P5 TDLY1 Delay between 4-bit Command and Command Operand
40
—
ns
P5A TDLY1A Delay between 4-bit Command Operand and
next 4-bit Command
40
—
ns
P6 TDLY2 Delay between Last PGC  of Command Byte to First
PGC  of Read of Data Word
20
—
ns
P9 TDLY5 PGC High Time (minimum programming time)
1
— ms Externally Timed
P9A TDLY5A PGC High Time
5
ms Configuration Word
programming time
P10 TDLY6 PGC Low Time after Programming
(high-voltage discharge time)
200
—
s
P11 TDLY7 Delay to allow Self-Timed Bulk Erase to occur PIC18(L)F
15
X5/X6
— ms
PIC18(L)F
12
X3/X4
— ms
P11A TDRWT Data Write Polling Time
4
— ms
P11B TDLY7B Delay for Self-Timed Memory Write
2
— ms
P12 THLD2 Input Data Hold Time from MCLR/VPP/RE3 
2
—
s
P13 TSET2 VDD Setup Time to MCLR/VPP/RE3 
100
—
ns
Note 1:
Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions
to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5
s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the
oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the
particular device.
DS41398B-page 38
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