PIC18LF2XK22 Datasheet, PDF (13/42 Pages) Microchip Technology – Flash Memory Programming Specification

3.0 DEVICE PROGRAMMING
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on code
memory, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately prior to a
program or erase.
3.1 ICSP Erase
3.1.1 HIGH-VOLTAGE ICSP BULK ERASE
Erasing code or data EEPROM is accomplished by
configuring two Bulk Erase Control registers located at
3C0004h and 3C0005h. Code memory may be erased
portions at a time, or the user may erase the entire
device in one action. Bulk Erase operations will also
clear any code-protect settings associated with the
memory block erased. Erase options are detailed in
Table 3-1. When any one or more blocks of code space
are code protected, then all code blocks will be erased
by default. If data EEPROM is code-protected
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).
TABLE 3-1: BULK ERASE OPTIONS
Description
Data
(3C0005h:3C0004h)
Chip Erase
Erase User ID
Erase Data EEPROM
Erase Boot Block
Erase Config Bits
Erase Code EEPROM Block 0
Erase Code EEPROM Block 1
Erase Code EEPROM Block 2
Erase Code EEPROM Block 3
0F8Fh
0088h
0084h
0081h
0082h
0180h
0280h
0480h
0880h
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
PIC18(L)F2XK22/4XK22
The code sequence to erase the entire device is shown
in Table 3-2 and the flowchart is shown in Figure 3-1.
Note:
A Bulk Erase is the only way to reprogram
code-protect bits from an “on” state to an
“off” state.
TABLE 3-2: BULK ERASE COMMAND
SEQUENCE
4-Bit
Data
Command Payload
Core Instruction
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
0F 0F
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 0Fh to 3C0005h
0000
0E 3C ^{MOVLW 3Ch}
0000
6E F8 ^{MOVWF TBLPTRU}
0000
0E 00 ^{MOVLW 00h}
0000
6E F7 ^{MOVWF TBLPTRH}
0000
0E 04 ^{MOVLW 04h}
0000
6E F6 ^{MOVWF TBLPTRL}
1100
0000
8F 8F
00 00
Write 8F8Fh TO 3C0004h
to erase entire device.
NOP
0000
00 00 ^{Hold PGD low until erase}
completes.
FIGURE 3-1:
BULK ERASE FLOW
Start
Write 0F0Fh
to 3C0005h
Write 8F8Fh to
3C0004h to Erase
Entire Device
Delay P11 + P10
Time
Done
 2010 Microchip Technology Inc.
Advance Information
DS41398B-page 13