PIC18LF2XK22 Datasheet, PDF(28/42 Page) Microchip Technology – Flash Memory Programming Specification

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PIC18LF2XK22 Datasheet, PDF (28/42 Pages) Microchip Technology – Flash Memory Programming Specification

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PIC18(L)F2XK22/4XK22

5.0 CONFIGURATION WORD

The PIC18(L)F2XK22/4XK22 devices have several

Configuration Words. These bits can be set or cleared

to select various device configurations. All other mem-

ory areas should be programmed and verified prior to

setting Configuration Words. These bits may be read

out normally, even after read or code protection. See

Table 5-1 for a list of Configuration bits and device IDs

and Table 5-3 for the Configuration bit descriptions.

5.1 User ID Locations

A user may store identification information (ID) in eight

ID locations mapped in 200000h:200007h. It is

recommended that the Most Significant nibble of each

ID be Fh. In doing so, if the user code inadvertently tries

to execute from the ID space, the ID data will execute

as a NOP.

5.2 Device ID Word

The device ID word for the PIC18(L)F2XK22/4XK22

devices is located at 3FFFFEh:3FFFFFh. These bits

may be used by the programmer to identify what device

type is being programmed and read out normally, even

after code or read protection. See Table 5-2 for a

complete list of device ID values.

FIGURE 5-1:

READ DEVICE ID WORD

FLOW

Start

Set TBLPTR = 3FFFFE

Read Low Byte

with Post-Increment

Read High Byte

with Post-Increment

Done

TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs

File Name

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default/

Unprogrammed

Value

300001h

300002h

300003h

300005h

300006h

300008h

300009h

30000Ah

30000Bh

30000Ch

30000Dh

3FFFFEh

3FFFFFh

Legend:

Note 1:

CONFIG1H IESO FCMEN PRI_CLK_EN PLLEN FOSC3 FOSC2 FOSC1 FOSC0 0010 0101

CONFIG2L â

BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111

CONFIG2H â

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 --11 1111

CONFIG3H MCLRE â

P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 1-11 1111

CONFIG4L DEBUG XINST

CONFIG5L â

CONFIG5H CPD CPB

CONFIG6L â

CONFIG6H WRTD WRTB

CONFIG7L â

WRTC

LVP

â STVREN 10-- -1-1

CP3(1) CP2(1)

CP1

CP0

---- 1111

11-- ----

WRT3(1) WRT2(1) WRT1 WRT0

---- 1111

111- ----

â EBTR3(1) EBTR2(1) EBTR1 EBTR0 ---- 1111

CONFIG7H

DEVID1(2)

DEVID2(2)

DEV2

DEV10

EBTRB

DEV1

DEV9

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

-1-- ----

See Table 5-2

x = unknown, u = unchanged, â = unimplemented. Shaded cells are unimplemented, read as â0â.

These bits are only implemented on specific devices. Refer to Section 2.3 âMemory Mapsâ to determine which bits

apply based on available memory.

DEVID registers are read-only and cannot be programmed by the user.

DS41398B-page 28

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