PIC18LF2XK22 Datasheet, PDF (10/42 Pages) Microchip Technology – Flash Memory Programming Specification

PIC18(L)F2XK22/4XK22
2.4 High-Level Overview of the
Programming Process
Figure 2-11 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 2-11:
HIGH-LEVEL
PROGRAMMING FLOW
Start
Perform Bulk
Erase
Program Memory
Program IDs
Program Data EE
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
2.5 Entering and Exiting High-Voltage
ICSP Program/Verify Mode
As shown in Figure 2-12, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/VPP/RE3 to VIHH
(high voltage). Once in this mode, the code memory,
data EEPROM, ID locations and Configuration bits can
be accessed and programmed in serial fashion.
Figure 2-13 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-12:
ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
P13
P12
P1
D110
MCLR/VPP/RE3
VDD
PGD
PGC
PGD = Input
FIGURE 2-13:
EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
P16
P17
MCLR/VPP/RE3
P1
D110
VDD
PGD
PGC
PGD = Input
DS41398B-page 10
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