PIC18LF2XK22 Datasheet, PDF (20/42 Pages) Microchip Technology – Flash Memory Programming Specification

PIC18(L)F2XK22/4XK22
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADRH:EEADR) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA with the data to be written and initiat-
ing a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 24th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must be held low for the time specified by parameter
P10 to allow high-voltage discharge of the memory
array.
FIGURE 3-6:
PROGRAM DATA FLOW
Start
Set Address
Set Data
Enable Write
Start Write
Sequence
WR bit
No
clear?
Yes
No
done?
Yes
Done
FIGURE 3-7:
DATA EEPROM WRITE TIMING DIAGRAM
12 3 4
1 2 15 16
PGC
P5
P5A
P5A
P11A
PGD ^{0 0 0 0}
4-bit Command BSF EECON1, WR
2 NOP commands
PGD = Input
Poll WR bit, Repeat until Clear
(see below)
P10
12
nn
16-bit Data
Payload
Poll WR bit
PGC
12 34
12
P5
15 16
1234
12
P5A
P5
15 16
P5A
PGD
0000
0000
4-bit Command MOVF EECON1, W, 0 4-bit Command
MOVWF TABLAT
PGD = Input
Shift Out Data
(see Figure 4-4)
PGD = Output
DS41398B-page 20
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