PIC18LF2XK22 Datasheet, PDF (31/42 Pages) Microchip Technology – Flash Memory Programming Specification

PIC18(L)F2XK22/4XK22
TABLE 5-3: PIC18(L)F2XK22/4XK22 BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
WDTPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
WDTEN<1:0> CONFIG2H Watchdog Timer Enable bits
11 = WDT enabled in hardware; SWDTEN bit is disabled
10 = WDT controlled by the SWDTEN bit
01 = WDT enabled when device is active, disabled when device is in Sleep;
SWDTEN bit is disabled
00 = WDT disabled in hardware; SWDTEN bit is disabled
MCLRE
CONFIG3H
MCLR Pin Enable bit
1 = MCLR pin enabled, RE3 input pin disabled
0 = RE3 input pin enabled, MCLR pin disabled
P2BMX
CONFIG3H
CCP2 B Output MUX bit
On 28-pin devices:
1 = P2B is on RB5
0 = P2B is on RC0
On 40-pin devices:
1 = P2B is on RD2
0 = P2B is on RC0
T3CMX
CONFIG3H 1 = T3CKI is on RC0
0 = T3CKI is on RB5
HFOFST
CONFIG3H
HFINTOSC Fast Start bit
1 = HFINTOSC output is not delayed
0 = HFINTOSC output is delayed until oscillator is stable (IOFS = 1)
CCP3MX
CONFIG3H CCP3 MUX bit
On 28-pin devices:
1 = CCP3 input/output is multiplexed with RB5
0 = CCP3 input/output is multiplexed with RC6
On 40-pin devices:
1 = CCP3 input/output is multiplexed with RB5
0 = CCP3 input/output is multiplexed with RE0
PBADEN
CONFIG3H PORTB A/D Enable bit
1 = PORTB A/D<5:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<5:0> pins are configured as digital I/O on Reset
CCP2MX
CONFIG3H
CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
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 2010 Microchip Technology Inc.
Advance Information
DS41398B-page 31