PIC18LF2XK22 Datasheet, PDF (27/42 Pages) Microchip Technology – Flash Memory Programming Specification

PIC18(L)F2XK22/4XK22
FIGURE 4-4:
SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010)
PGC
1234
12 3 45 6 78
(Note 1)
9 10 11 12 13 14 15 16
1 234
P5
P6
P5A
P14
PGD
0100
LSb 1 2 3 4 5 6
(Note 1)
MSb n n n n
PGD = Input
Shift Data Out
PGD = Output
Note 1: Magnification of the High-Impedance delay between PGC and PGD is shown in Figure 4-5.
Fetch Next 4-bit Command
PGD = Input
FIGURE 4-5:
PGC
HIGH-IMPEDANCE DELAY
P3
1
2
PGD _MSb
n
n
P19
4.5 Verify Data EEPROM
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
4.6 Blank Check
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’.
Therefore, Blank Checking a device merely means to
verify that all bytes read as FFh except the Configura-
tion bits. Unused (reserved) Configuration bits will read
‘0’ (programmed). Refer to Table 5-1 for blank configu-
ration expect data for the various PIC18(L)F2XK22/
4XK22 devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 “Read Data EEPROM Memory” and
Section 4.2 “Verify Code Memory and ID Locations”
for implementation details.
FIGURE 4-6:
BLANK CHECK FLOW
Start
Blank Check Device
Is
device
blank?
No
Abort
Yes
Continue
 2010 Microchip Technology Inc.
Advance Information
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