PIC18LF2XK22 Datasheet, PDF (14/42 Pages) Microchip Technology – Flash Memory Programming Specification

PIC18(L)F2XK22/4XK22
FIGURE 3-2:
BULK ERASE TIMING DIAGRAM
PGC
12 3 4
12
P5
15 16
1234
12
P5A
P5
15 16
1234
P5A
P10
12
P11
PGD 0 0 1 1
4-bit Command
11 00
16-bit
Data Payload
00 00
00 00
0000
4-bit Command
16-bit
Data Payload
PGD = Input
4-bit Command
Erase Time
nn
16-bit
Data Payload
3.1.2 LOW-VOLTAGE ICSP BULK ERASE
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.3 “ICSP Row Erase” and Section 3.2.1
“Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.3
“Data EEPROM Programming” and write ‘1’s to the
array.
3.1.3 ICSP ROW ERASE
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data),
provided the block is not code or write-protected. Rows
are located at static boundaries beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 2.3 “Memory
Maps”).
The Row Erase duration is self-timed. After the WR bit
in EECON1 is set, two NOPs are issued. Erase starts
upon the 4th PGC of the second NOP. It ends when the
WR bit is cleared by hardware.
The code sequence to Row Erase is shown in Table 3-3.
The flowchart shown in Figure 3-3 depicts the logic
necessary to completely erase the device. The timing
diagram for Row Erase is identical to the data EEPROM
write timing shown in Figure 3-7.
Note: The TBLPTR register can point at any byte
within the row intended for erase.
DS41398B-page 14
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