PIC16F1829LIN Datasheet, PDF(53/74 Page) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

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PIC16F1829LIN Datasheet, PDF (53/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

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PIC16F1829LIN

8.2 Asynchronous Reception Setup

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 26.3, EUSART

Baud Rate Generator (BRG) in the

âPIC16(L)F1825/1829 Data Sheetâ (DS41440)).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

APFCON0 RXDTSEL

T1GSEL TXCKSEL

BAUDCON ABDOVF RCIDL

SCKP BRG16

WUE ABDEN

INLVLA

INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0

INLVLB

INLVLB7 INLVLB6 INLVLB5 INLVLB4

INLVLC

INTCON

PIE1

PIR1

INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 47

GIE

PEIE TMR0IE INTE

IOCIE TMR0IF

INTF

IOCIF

TMR1GIE ADIE

RCIE

TXIE SSP1IE CCP1IE TMR2IE TMR1IE

TMR1GIF ADIF

RCIF

TXIF SSP1IF CCP1IF TMR2IF TMR1IF

RCREG

EUSART Receive Data Register

53*

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR

OERR

RX9D

SPBRGL

BRG<7:0>

52, 53*

SPBRGH

BRG<15:8>

TRISA

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

TRISB

TRISB7 TRISB6 TRISB5 TRISB4

TRISC

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

TXSTA

CSRC

TX9

TXEN

SYNC SENDB BRGH

TRMT

TX9D

Legend: â = unimplemented location, read as â0â. Shaded cells are not used for Asynchronous Reception.

* Page provides register information.

52, 53*

ï£ 2012 Microchip Technology Inc.

Preliminary

DS41673A-page 53

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