PIC16F1829LIN Datasheet, PDF (22/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

TABLE 4-1: PIC16F1829LIN MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
000h
INDF0
080h
INDF0
100h
INDF0
180h
INDF0
001h
INDF1
081h
INDF1
101h
INDF1
181h
INDF1
002h
PCL
082h
PCL
102h
PCL
182h
PCL
003h
STATUS
083h
STATUS
103h
STATUS
183h
STATUS
004h
FSR0L
084h
FSR0L
104h
FSR0L
184h
FSR0L
005h
FSR0H
085h
FSR0H
105h
FSR0H
185h
FSR0H
006h
FSR1L
086h
FSR1L
106h
FSR1L
186h
FSR1L
007h
FSR1H
087h
FSR1H
107h
FSR1H
187h
FSR1H
008h
BSR
088h
BSR
108h
BSR
188h
BSR
009h
WREG
089h
WREG
109h
WREG
189h
WREG
00Ah
PCLATH
08Ah
PCLATH
10Ah
PCLATH
18Ah
PCLATH
00Bh
INTCON
08Bh
INTCON
10Bh
INTCON
18Bh
INTCON
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTB
PORTC
—
—
PIR1
PIR2
—
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
—
CPSCON0
CPSCON1
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
TRISB
TRISC
—
—
PIE1
PIE2
—
—
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
LATB
LATC
—
—
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
APFCON0
APFCON1
—
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
ANSELB
ANSELC
—
—
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
—
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
BAUDCON
06Fh
070h
07Fh
General
Purpose
Register
96 Bytes
0EFh
0F0h
0FFh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
16Fh
170h
17Fh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
1EFh
1F0h
1FFh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
26Fh
270h
27Fh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’
Registers in bold have functional differences. Please refer to the appropriate chapters for details.
BANK 4
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
WPUB
WPUC
—
—
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON
SSP1CON2
SSP1CON3
—
SSP2BUF
SSP2ADD
SSP2MSK
SSP2STAT
SSP2CON
SSP2CON2
SSP2CON3
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
BANK 5
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS
—
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
36Fh
370h
37Fh
BANK 6
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR3L
CCPR3H
CCP3CON
—
—
—
—
CCPR4L
CCPR4H
CCP4CON
—
—
—
—
—
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INLVLA
INLVLB
INLVLC
—
—
IOCAP
IOCAN
IOCAF
IOCBP
IOCBN
IOCBF
—
—
—
CLKRCON
—
MDCON
MDSRC
MDCARL
MDCARH
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh