PIC16F1829LIN Datasheet, PDF (32/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

PIC16F1829LIN
TABLE 4-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 5
280h⁽¹⁾ INDF0
281h⁽¹⁾ INDF1
282h⁽¹⁾
283h⁽¹⁾
284h⁽¹⁾
285h⁽¹⁾
286h⁽¹⁾
287h⁽¹⁾
288h⁽¹⁾
289h⁽¹⁾
28Ah⁽¹⁾
28Bh⁽¹⁾
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
28Ch
—
Unimplemented
—
—
28Dh
—
Unimplemented
—
—
28Eh
—
Unimplemented
—
—
28Fh
—
Unimplemented
—
—
290h
—
Unimplemented
—
—
291h CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
292h CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
293h CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
0000 0000 0000 0000
294h PWM1CON P1RSEN
P1DC<6:0>
0000 0000 0000 0000
295h CCP1AS
CCP1ASE
CCP1AS<2:0>
PSS1AC<1:0>
PSS1BD<1:0>
0000 0000 0000 0000
296h PSTR1CON
—
—
—
STR1SYNC STR1D
STR1C
STR1B
STR1A ---0 0001 ---0 0001
297h
—
Unimplemented
—
—
298h CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
299h CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
29Ah CCP2CON
P2M1
P2M0
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
29Bh PWM2CON
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC2
P2DC1
P2DC0 0000 0000 0000 0000
29Ch CCP2AS
CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
29Dh PSTR2CON
29Eh⁽²⁾ CCPTMRS
—
—
—
STR2SYNC STR2D
STR2C
STR2B
STR2A ---0 0001 ---0 0001
0
C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details.
DS41673A-page 32
Preliminary
 2012 Microchip Technology Inc.