PIC16F1829LIN Datasheet, PDF (52/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

PIC16F1829LIN
8.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It functions the same as
described in the “PIC16(L)F1825/1829 Data Sheet”
(DS41440) with the following differences:
• The 9-bit character length and Address detection
should not be used.
• Programmable clock and data polarity should not
be used.
8.1 Asynchronous Transmission
Setup
1. Initialize the SPBRGH, SPBRGL register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 26.3, EUSART Baud
Rate Generator (BRG) in the
“PIC16(L)F1825/1829 Data Sheet” (DS41440)).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. TX9 control bit should always be ‘0’ for LIN
transmission.
4. Set the SCKP bit if inverted transmit is desired.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately, provided that the GIE and
PEIE bits of the INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON0 RXDTSEL —
—
— T1GSEL TXCKSEL —
—
38
BAUDCON ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
56
INLVLA
—
— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
—
INLVLB
INLVLB7 INLVLB6 INLVLB5 INLVLB4 —
—
—
—
43
INLVLC
INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 47
INTCON
GIE
PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF
—
PIE1
PIR1
TMR1GIE ADIE RCIE
TXIE SSP1IE CCP1IE TMR2IE TMR1IE
—
TMR1GIF ADIF
RCIF
TXIF SSP1IF CCP1IF TMR2IF TMR1IF
—
RCSTA
SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D
55
SPBRGL
BRG<7:0>
52*
SPBRGH
TRISA
TRISB
TRISC
BRG<15:8>
52*
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
—
TRISB7 TRISB6 TRISB5 TRISB4
—
—
—
—
41
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
45
TXREG
EUSART Transmit Data Register
52*
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
54
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
* Page provides register information.
DS41673A-page 52
Preliminary
 2012 Microchip Technology Inc.