PIC16F1829LIN Datasheet, PDF (27/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

PIC16F1829LIN
TABLE 4-6: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
000h⁽¹⁾ INDF0
001h⁽¹⁾ INDF1
002h⁽¹⁾
003h⁽¹⁾
004h⁽¹⁾
005h⁽¹⁾
006h⁽¹⁾
007h⁽¹⁾
008h⁽¹⁾
009h⁽¹⁾
00Ah⁽¹⁾
00Bh⁽¹⁾
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
INTF
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
C
IOCIF
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
00Ch
00Dh⁽²⁾
00Eh⁽²⁾
PORTA
PORTB
PORTC
—
LINTX
PWRGD
—
LINCS
—
RA5
LINRX
RC5
RA4
RB4
RC4
RA3
—
RC3
RA2
—
RC2
RA1
—
RC1
RA0
—
RC0
--xx xxxx --xx xxxx
xxxx ---- xxxx ----
xxxx xxxx xxxx xxxx
00Fh —
Unimplemented
—
—
010h —
Unimplemented
—
—
011h PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
CCP2IF 0000 0--0 0000 0--0
013h PIR3
—
—
CCP4IF
CCP3IF TMR6IF
—
TMR4IF
—
--00 0-0- --00 0-0-
014h PIR4
—
—
—
—
—
—
BCL2IF SSP2IF ---- --00 ---- --00
015h TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
016h TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
017h TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
018h T1CON
TMR1CS1 TMR1CS0
T1CKPS<1:0>
T1OSCEN T1SYNC
—
TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON
TMR1GE T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
0000 0x00 uuuu uxuu
01Ah TMR2
Timer2 Module Register
0000 0000 0000 0000
01Bh PR2
Timer2 Period Register
1111 1111 1111 1111
01Ch T2CON
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
-000 0000 -000 0000
01Dh —
Unimplemented
—
—
01Eh CPSCON0
CPSON
CPSRM
—
—
CPSRNG<1:0>
CPSOUT T0XCS 00-- 0000 00-- 0000
01Fh CPSCON1
—
—
—
—
CPSCH<3:0>
---- 0000 ---- 0000
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details.
 2012 Microchip Technology Inc.
Preliminary
DS41673A-page 27