PIC16F1829LIN Datasheet, PDF (30/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

PIC16F1829LIN
TABLE 4-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 3
180h⁽¹⁾ INDF0
181h⁽¹⁾ INDF1
182h⁽¹⁾
183h⁽¹⁾
184h⁽¹⁾
185h⁽¹⁾
186h⁽¹⁾
187h⁽¹⁾
188h⁽¹⁾
189h⁽¹⁾
18Ah⁽¹⁾
18Bh⁽¹⁾
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
—
—
—
TO
PD
Z
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR<4:0>
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
DC
INTF
C
IOCIF
18Ch
18Dh⁽²⁾
18Eh⁽²⁾
ANSELA
ANSELB
ANSELC
—
ANSB7
ANSC7
—
ANSB6
—
—
ANSB5
—
ANSA4
ANSB4
—
—
—
ANSC3
ANSA2
—
ANSC2
ANSA1
—
ANSC1
ANSA0
—
ANSC0
18Fh
—
Unimplemented
190h
—
Unimplemented
191h EEADRL
EEPROM / Program Memory Address Register Low Byte
192h EEADRH
—
EEPROM / Program Memory Address Register High Byte
193h EEDATL
EEPROM / Program Memory Read Data Register Low Byte
194h EEDATH
—
—
EEPROM / Program Memory Read Data Register High Byte
195h EECON1
EEPGD
CFGS
LWLO
FREE
WRERR WREN
WR
RD
196h EECON2
EEPROM control register 2
197h
—
Unimplemented
198h
—
Unimplemented
199h RCREG
EUSART Receive Data Register
19Ah TXREG
EUSART Transmit Data Register
19Bh SPBRGL
BRG<7:0>
19Ch SPBRGH
BRG<15:8>
19Dh RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
19Eh TXSTA
19Fh⁽²⁾ BAUDCON
CSRC
ABDOVF
TX9
RCIDL
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDEN
Legend:
Note 1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details.
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
---1 -111 ---1 -111
1111 ---- 1111 ----
11-- 1111 11-- 1111
—
—
—
—
0000 0000 0000 0000
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
0000 x000 0000 q000
0000 0000 0000 0000
—
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
01-0 0-00 01-0 0-00
DS41673A-page 30
Preliminary
 2012 Microchip Technology Inc.