PIC16F1829LIN Datasheet, PDF(28/74 Page) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

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PIC16F1829LIN Datasheet, PDF (28/74 Pages) Micon Design Technology Corporation – 20-Pin, 8-bit Flash LIN/J2602 Microcontroller

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PIC16F1829LIN

TABLE 4-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other

Resets

Bank 1

080h(1) INDF0

081h(1) INDF1

082h(1)

083h(1)

084h(1)

085h(1)

086h(1)

087h(1)

088h(1)

089h(1)

08Ah(1)

08Bh(1)

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

â

â

â

TO

PD

Z

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

â

â

â

BSR<4:0>

Working Register

â

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

DC

INTF

xxxx xxxx xxxx xxxx

xxxx xxxx xxxx xxxx

C

IOCIF

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 0000 0000 0000

08Ch

08Dh(2)

08Eh(2)

TRISA

TRISB

TRISC

â

TRISB7

TRISC7

â

TRISB6

TRISC6

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA3

â

TRISC3

TRISA2

â

TRISC2

TRISA1

â

TRISC1

TRISA0

â

TRISC0

--11 1111 --11 1111

1111 ---- 1111 ----

1111 1111 1111 1111

08Fh

â

Unimplemented

â

â

090h

â

091h(2) PIE1

Unimplemented

TMR1GIE

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

â

â

TMR1IE 0000 0000 0000 0000

092h PIE2

OSFIE

C2IE

C1IE

EEIE

BCL1IE

â

â

CCP2IE 0000 0--0 0000 0--0

093h PIE3

094h(2) PIE4

â

â

CCP4IE

CCP3IE TMR6IE

â

TMR4IE

â

--00 0-0- --00 0-0-

â

â

â

â

â

â

BCL2IE SSP2IE ---- --00 ---- --00

095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE

PSA

PS<2:0>

1111 1111 1111 1111

096h PCON

STKOVF STKUNF

â

â

RMCLR

RI

POR

BOR 00-- 11qq qq-- qquu

097h WDTCON

â

â

WDTPS<4:0>

SWDTEN --01 0110 --01 0110

098h OSCTUNE

â

â

TUN<5:0>

--00 0000 --00 0000

099h OSCCON

SPLLEN

IRCF<3:0>

â

SCS<1:0>

0011 1-00 0011 1-00

09Ah OSCSTAT

T1OSCR

PLLR

OSTS

HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q

09Bh ADRESL

A/D Result Register Low

xxxx xxxx uuuu uuuu

09Ch ADRESH

A/D Result Register High

xxxx xxxx uuuu uuuu

09Dh ADCON0

â

CHS<4:0>

GO/DONE ADON -000 0000 -000 0000

09Eh ADCON1

ADFM

ADCS<2:0>

â

ADNREF

ADPREF<1:0>

0000 -000 0000 -000

09Fh

â

Unimplemented

â

â

Legend:

Note 1:

2:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as â0â.

These registers can be addressed from any bank.

Registers in bold have functional differences. Please refer to the appropriate chapters in the data sheet for details.

DS41673A-page 28

Preliminary

ï£ 2012 Microchip Technology Inc.

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