MAX11253 Datasheet, PDF (8/51 Pages) Maxim Integrated Products – Longer Battery Life for Portable Applications

MAX11253
16-Bit, 6-Channel, 64ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with SPI Interface
SPI Timing Requirements
(V_AVDD = 3.6V, V_AVSS = 0V, V_DVDD = 1.7V to 3.6V, T_A = T_MIN to T_MAX, unless otherwise noted. For output pins, C_LOAD = 20pF.)
PARAMETER
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CSB Low Setup
CSB High Setup
SCLK Fall Hold
CSB Pulse Width
DIN Setup
DIN Hold
DOUT Transition
DOUT Hold
DOUT Disable
CSB Fall to DOUT Valid
SCLK Rise to RDYB ‘1’
SYMBOL
CONDITIONS
MIN
f_SCLK
Note 5 applies to minimum value
0.05
t_CP
125
t_CH
Allow 40% duty cycle
50
t_CL
Allow 40% duty cycle
50
t_CSS0
CSB low to 1st SCLK rise setup
40
t_CSS1
CSB rising edge to SCLK rising edge
setup time (Note 5)
40
t_CSH1
SCLK falling edge to CSB rising edge,
SCLK hold time
3
t_CSW
Minimum CSB pulse-width high
40
t_DS
DIN setup to SCLK rising edge
40
t_DH
DIN hold after SCLK rising edge
0
t_DOT
DOUT transition valid after SCLK fall
(Note 5)
t_DOH
Output hold time remains valid after
SCLK fall (Note 5)
3
t_DOD
CSB rise to DOUT disable (Note 5)
t_DOE
(Note 5)
0
RDYB transitions from ‘0’ to ‘1’ on
t_R1
rising edge of SCLK when LSB-1 of
0
DATA is shifted onto DOUT (Note 5)
TYP
MAX
UNITS
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
ns
ns
25
ns
40
ns
40
ns
RSTB Fall to RDYB ‘1’
RDYB transition from ‘0’ to ‘1’ on
falling edge of RSTB, internal clock
mode (Note 5)
t_R2
RDYB transition from ‘0’ to ‘1’ on
falling edge of RSTB, external clock
mode, clock frequency = f_CLK
(Note 5)
300
ns
2/f_CLK
s
Note 2: Limits are 100% tested at T_A = +25°C, unless otherwise noted. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization.
Note 3: Full-scale error includes errors from gain and offset or zero-scale error.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: These specifications are guaranteed by design, characterization, or SPI protocol.
Note 6: Reference common mode (V_REFP + V_REFN)/2 ≤ (V_AVDD + V_AVSS)/2 + 0.1V.
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